Most known flash memories are electrically erasable programmable read only memories (EEPROM) that support three operations: read, program and erase. Flash-type memories have a structure in which the edges of a source region and a drain region overlap a floating gate with a thin tunnel oxide layer therebetween. Flash memories are popular over traditional EEPROMs because the flash cell size is less than the EEPROM cell size, and flash memories are popular over EPROMs because the flash memory can be electrically erased without the need to expose the memory to UV light.
Flash memories are typically constructed as a NOR-plane array. When any of the transistors in the NOR-plane turns on, the drain current is changed on the bitline and a current sense amplifier detects the current change and converts the change to a data output. There are two erasing procedures for the NOR-plane flash memories. A first approach uses the voltages shown in Table 1 for erase, program and read. A flash EEPROM of this type is explained in Yim et at, U.S. Pat. No. 5,109,361.
TABLE 1 ______________________________________ mode gate source drain ______________________________________ erase VSS (ground) VPPA (+13V) float program VPP (+10V) VSS (ground) VPI (+5-7V) read VPI (+5V) VSS (ground) &lt;VDD (&lt;+1V) ______________________________________
A second approach uses erase voltages shown in Table 2. The second approach uses identical voltages for program and read.
TABLE 2 ______________________________________ mode gate source drain ______________________________________ erase VNN (-10V) VPI (+5V) float ______________________________________
The present invention can employ the voltage levels of either approach, but the detailed description gives an example using the voltages of the second approach.
In flash memories using the voltages of the first approach, a known flash memory provides the ability to erase the entire memory array or a large sector of approximately 128K bytes. Once the array is erased, it is re-programmed with the new data. The second approach provides an additional capability called a page-erase that can erase typically 512 or 128 bytes, which is smaller than in the first approach. Although the page-erase feature provides a much smaller erase size, it does not provide a high level of erase selectivity that is desired in order to promote fast operation.
A problem with known flash EEPROMs is that they have a slow operation because in order to write to the memory, an entire page of memory is erased and then programmed. This is true even if only a small portion is changed. As a result, the page-erase feature causes undue delays in changing the information in the flash memory and can cause delays in regaining access to the flash memory.
Additionally, there is a great desire to develop a flash memory having a long life. One problem with existing flash memories is low expected lifetime. Whenever an erase is performed on a flash transistor, the transistor is stressed, which reduces the life of the transistor. A result of the page-erase feature is that the erase operation stresses all the transistors in the page. Over time, the stress reduces the flash memory life. For example, it is very difficult to build a flash memory that can survive 10 6 write/erase cycles due to the erase and program stress on the flash memory cells. Therefore, a method of reducing stress in a flash memory is a very important development.
A goal of the invention is to overcome the identified problems and to provide a new technique to select a flexible-byte of flash cells to be erased. In an exemplary embodiment, the minimum erase size is one byte without sacrificing the array size. The invention provides that unnecessary write/erase cycles are not performed on the deselected cells. As a result, a the invention can provide a large number of operable write/erase cycles, such as 10 6 write/erase cycles, in a flash memory.